This invention relates to high frequency semiconductor devices and methods for their fabrication, and especially to improved vertical channel field effect transistor structures isolated by using high energy electron, neutron or proton bombardment.
Vertical channel FETs have been made out of silicon to operate at high voltages and high current levels. However, the power handling capability of a gallium arsenide device with the same area is expected to be higher. The vertical FET in U.S. Pat. No. 4,129,879 to W. Tantraporn and S. P. Yu has the channel regions in elongated fingers upstanding from the substrate which is the common source or drain; gate metal surrounds the finger and forms an electronically blocking contact to the channel which extends completely across the finger from wall to wall without interruption. Copending application Ser. No. 061,450 filed on July 27, 1979 by J. R. Shealy, B. J. Baliga, W. Tantraporn and P.V. Gray, now issued as U.S. Pat. No. 4,262,296, covers an improved vertical FET of gallium arsenide or other III-V semiconductor which has a preferentially etched groove structure in the top surface which yields parallel trapezoidal semiconductor fingers that are wider at the top than at the bottom. Gate regions are fabricated in the grooves surrounding the fingers. The vertical conducting channels are narrow leading to a high blocking gain and more contact area is available at the top of the device.
The performance of the latter high frequency device is limited by the following. The active area of the device must be properly terminated in order to get high gate-drain breakdown voltages. Second, the gate contact pad adds a significant parasitic capacitance. Third, the device contains individual source (or drain) fingers which are isolated from each other by the etching of the trapezoidal grooves. These are mechanically fragile and need to be connected together during device packaging, and this is expected to lower the yield and increase the contact resistance.